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| DATA SHEET MOS INTEGRATED CIRCUIT PD16667 160-OUTPUT LCD ROW DRIVER The PD16667 is a row (common) driver which contains a RAM capable of full-dot LCD display. With 160 outputs, this driver can be combined with a column (segment) driver, PD16662, which contains a RAM to display 240 x 160 pixels to 480 x 320 pixels. With a built-in display RAM, the column driver can reduce the current consumption, thus making it most suitable for the display block of a PDA or portable terminal. FEATURES * * * * * LCD-driven voltage: 20 to 36 V Duty: 1/160 Driving type: 2 lines selected simultaneously Output count: 160 outputs Capable of gray scale display: 4 gray scales ORDERING INFORMATION Part No. Package TCP (TAB) Standard TCP (OLB: 0.2 mm pitch, folding) PD16667N-XXX PD16667N-051 The external shape of the TCP is custom-made, so please contact an NEC sales representative with your shape requirements. Document No. S12838EJ4V0DS00 (4th edition) Date Published January 1999 N CP(K) Printed in Japan The mark shows major revised points. PD16667 BLOCK DIAGRAM X1 to X160 VDD Liquid-crystal drive circuit V1 VEE Selection control circuit Q1 to Q80 Bidirectional shift register DIR VCC1 VSS Level shifter L1 L2 /DOFF' STB /FRM Remark /xxx indicates active low signal. Column driver interface BLOCK FUNCTION 1. Liquid-crystal drive circuit This circuit selects and outputs the level for liquid-crystal driving. One of VDD, VEE, and V1 is selected by the output of the selection control circuit. 2. Selection control circuit This circuit creates the signal which will select the level of the output signal, based on the output of the shift register circuit and the driving level power selection signals L1 and L2 3. Bidirectional shift register circuit This refers to the 80-bit bidirectional shift register circuit. The DIR signal can be used to switch over the shift direction. The data that has been entered from the /FRM pin is shifted by the low drive signal strobe (STB). 4. Level shifter circuit This circuit transforms the 5-V signals to the high-voltage signals for liquid-crystal driving. 2 PD16667 PIN FUNCTIONS Classification Power suuply Pin Name VCC1 VSS VDD VEE V1 STB /FRM /DOFF' L1 L2 DIR X1 to X160 I I I I I I O Input/Output Pad No. Function 5 V power for level shifter GND for level shifter Power for logic, liquid-crystal drive level power Power for logic, liquid-crystal drive level power (GND) Liquid-crystal drive level power Row drive signal strobe Frame signal Display OFF signal Drive level power selection symbol (1st line) Drive level power selection symbol (2nd line) Shift direction selection symbol:when L (DIR = VEE), X1 X160 when H (DIR = VDD), X160 X1 Liquid-crystal drive output Selects and outputs one of VDD, VEE, and V1. Liquid-crystal display timing Liquid-crystal drive output DETAILS OF PIN FUNCTIONS * STB (input) Input pin of the row drive strobe signal The bidirectional shift register is shifted at STB's rising edge. /FRM (input) Input pin of the frame signal The shift register data is read at STB's rising edge. DIR (input) Input pin of the drive output's shift direction selection signal When the shift direction selection signal (DIR) is "L", the shift data (selection signal) is shifted from the drive output X1 to the X160 direction. When "H", it is shifted from the X160 to the X1 direction. /DOFF' (input) Input pin of the display OFF signal It is placed in the display OFF status (all outputs at V1) at the "L" level. In the mean time, it reads the frame signal and returns to the normal display status at the "H" level. L1 and L2 (input) Input pins of the drive level power selection signal In the case of the liquid-crystal drive output, the two lines are selected simultaneously by the shift register. L1 selects the first line, and L2 selects the second line. Both lines select VDD at "H", and VEE at "L". * * * * 3 PD16667 SYSTEM CONFIGURATION EXAMPLE This example shows configuration of a liquid-crystal panel of half-VGA size (480 x 320 oblong) using four column drivers and two row drivers. * * * * * * Each column driver sets the LSI No. with PL0 and PL1 pins. The DIR pins of each column driver are all set to low level. Only one of the column drivers is set to the master, all the others are set to the slave. Signals are supplied from the master column driver to the slave column driver and the row driver. Connect an oscillator resistor to the OSC1 and OSC2 pins of the master, and leave the slave open. Inputs signals from the system (D0 to D15, A0 to A16, /CS, /OE, /WE, /UBE, RDY, /RESET, /DOFF') in parallel to all of the column driver. Connect a pull-up resistor to the RDY signal. The TEST pin is used to test the LSI, and is open or GND when the system is configured. VCC2 PULSE STB /FRM /DOUT, /DOFF' L1 L2 /REFRH Y1 Row driver RDY /DOFF /RESET D0 to D15 A0 to A16 Control (/CS, /OE, /WE, /UBE) OSC1 Master No. 0 OSC2 Slave No. 2 Y240 Y240 Y1 Scan direction Scan direction 160 Row driver 160 Y240 Slave No. 1 Y1 Y240 Slave No. 3 Y1 Remark The /DOUT pin is an output pin for the column driver. 4 PD16667 POWER SUPPLY SEQUENCE OF CHIP SET It is recommended to apply power in the following sequence. VCC2 VCC1 input VDD, VEE V1, V2 Be sure to apply LCD drive voltages V1 and V2 last. ON VCC2 Note 1 OFF ON VCC1 OFF 4.5 V CPU I/F Note 1 0 s or more 0V 3.3 V (A0 to A16, /CS, /OE, /WE, /UBE, D0 to D15, /DOFF) 3.3 V /RESET Note 1 0V 0.3 VCC2 100 ns or more 0 s or more ON VDDNote 2 OFF OFF VEE Note 2 ON 0 ns or more ON V1 OFF ON V2 Note 1 OFF Notes 1. VCC2, CPU I/F, /RESET, and V2 are column driver power supply pins or input pins. 2. VDD and VEE do not need to be turned ON at the same time. Caution Turn off the power to the chip set in the reverse order of the power application sequence. 5 PD16667 EXAMPLE OF CONNECTING INTERNAL SCHOTTKY BARRIER DIODE OF MODULE TO REINFORCE POWER SUPPLY PROTECTION (Use a schottky barrier diode with Vf = 0.5 V or less.) VDD VCC1 V2 Note V1 V0 Note VSS VEE Connect the diodes enclosed in the dotted line ( ) when V0 is not 0 V (GND) Note V0 and V2 are column driver liquid-crystal power supplies. 6 PD16667 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 C, VSS = 0 V) Parameter Supply voltage Symbol VCC1 VDD - VEE V1 Input voltage VI1 VI2 Output voltage Operating temperature Storage temperature VO TA Tstg Other than the DIR pin DIR pin VCC1 VDD, VEE VSS Condition Ratings -0.5 to +6.5 40 VEE - 0.5 to VDD + 0.5 -0.5 to VCC1 + 0.5 VEE - 0.5 to VDD + 0.5 VEE - 0.5 to VDD + 0.5 -20 to +70 -40 to +125 C Unit V Recommended Operating Range (TA = -20 to +70 C, VSS = 0 V) Parameter Supply voltage Symbol VCC1 VDD - V1 V1 - VEE V1 Input voltage VI1 VI2 Other than DIR pin DIR pin Condition MIN. 4.75 10 10 0 0 VEE TYP. MAX. 5.25 18 18 3 VCC1 VDD Unit V DC Characteristics (unless otherwise specified, VCC1 = 4.75 to 5.25 V, VDD - (VEE) = 20 to 31 V, VCC1 VDD, VEE VSS, V1 = 0 to 3 V, VSS = 0 V, TA = - 20 to +70 C) Parameter High-level input voltage Symbol VIH1 VIH2 Low-level input voltage VIL1 VIL2 Driver ON resistance Input leakage current RON IIH1 IIH2 IIL1 IIL2 Current consumption ICC1 IDD Condition Other than the DIR pin DIR pin Other than the DIR pin DIR pin Load current = 100 A VIN = VCC, other than the DIR pin VIN = VDD, DIR pin VIN = 0 V, other than the DIR pin VIN = VEE, DIR pin Operating frame frequency at 70 Hz 200 40 1.0 MIN. 0.8 VCC1 VDD - 0.3 (VDD - VEE) 0.2 VCC1 VEE + 0.3 (VDD - VEE) 2.0 1.0 25 -1.0 -25 320 100 k TYP. MAX. Unit V A A 7 PD16667 AC Characteristics Parameter STB high-level width STB low-level width /FRM setup time /FRM hold time STB rising time STB falling time Output delay time Symbol twsh twsl tsf thf tr tf tpdsx tpdout Output no-load Condition MIN. 500 500 100 100 150 150 300 200 TYP. MAX. Unit ns 8 PD16667 AC CHARACTERISTICS WAVEFORM DIAGRAMS tr VCC1 0.9 VCC1 STB VSS 0.1 VCC1 0.5 VCC1 twsh twsl tsf VCC1 /FRM VSS 0.5 VCC1 thf tf VCC1 /DOFF' VSS tpdsx VDD VDD to V1 50 % Xn V1 VEE to V1 50 % VEE tpdsx VDD VDD to V1 50 % Xn + 2 V1 VEE to V1 50 % VEE tpdout tpdsx tpdout tpdsx 0.5 VCC1 9 PD16667 LEVEL SELECTION TIMING OF LIQUID-CRYSTAL DRIVE OUTPUT The /FRM is input twice in one frame. The STB is input 81 times in half a frame, and 162 times in one frame. VDD DIR /FRM STB VEE VCC1 VSS VCC1 VSS 81 1 2 80 81 1 2 80 81 1 2 80 81 1 2 80 81 1 frame T1 VCC1 T2 T3 T4 L1 L2 VSS VCC1 VSS VDD X1 V1 VEE X2 X3 X4 X160 (When DIR is "H") VDD DIR VEE VDD X160 V1 VEE X159 X158 X157 X1 Remark When /DOFF' is "L", the X output becomes V1 level. Afterward, if /DOFF' becomes "H", the level of the X output is output with the above timing. When the time difference between the STB, L1, and L2 signals is large, hazards may occur in output. Caution 10 PD16667 STANDARD TCP PACKAGE (PD16667N-051) 11 PD16667 Detail of cross mark 0.30.05 0.050.02 0.60.05 0.050.02 TCP tape winding direction Output leads Winding direction Unwinding direction CU pattern is on the backside of the tape 12 PD16667 PIN CONFIGURATION NC VEE V1 VDD VEE VSS VCC1 VDD /FRM /DOUT L1 L2 STB DIR VEE VDD V1 VEE NC NC NC NC Y1 Y2 Y3 Y4 Y5 * * * * * * * * * * PD16667N -051 * * * * * * * * * * * * * * Y156 Y157 Y158 Y159 Y160 NC NC NC 13 PD16667 [MEMO] 14 PD16667 [MEMO] 15 PD16667 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5 |
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